1. Field of the Invention
This invention relates to digital data processing systems. More specifically it relates to the interconnection of various units in such a system and the transfer of data among those units.
2. Description of the Prior Art
A digital data processing system comprises three basic elements: namely, a memory element, an input/output element and a processor element. The memory stores information in uniquely-identifiable addressable storage locations. This information includes data and instructions for processing the data. The processor unit transfers information to and from the memory element, interprets the incoming information as either data or instructions, and processes the data in accordance with the instructions. The input/output element also communicates with the memory element in order to transfer data into the system and to obtain processed data from it.
Over the years a number of arrangements have been devised for interconnecting the various elements of the data processing system. For example, U.S. Pat. No. 3,710,634 discloses an arrangement in which the processor element, memory element and input/output element are all connected to a common bus over which each element communicates with the others. The input-output element may, however, comprise a number of units, each of which may communicate over the bus. This can result in the processor being delayed a considerable length of time if it needs to make a transfer to memory to obtain data or an instruction.
As a result, an arrangement was devised in which the prior common bus was retained, but in which a bus was added directly connecting the processor element and at least a portion of the memory element. This arrangement is disclosed in U.S. Pat. No. 4,016,541. The processor may thus communicate directly with the memory element over its dedicated bus, as well as over the common bus. The processor may communicate with the input/output element only over the common bus, however. Thus, the processor element and the memory element are required to contain interfacing circuitry to permit them to communicate over two busses, the dedicated bus and the common bus. Furthermore, while the memory element normally will communicate over the bus from which it receives communications from the processor element or the input/output elements, the processor element itself must determine which bus it will use for communications with the memory element, which further increases the circuitry required in the processor.